The present invention relates in general to a phase locked loop circuit, especially in an integrated circuit.
When a phase locked loop circuit (PLL) is incorporated in an integrated circuit, where the PLL shares a substrate with other circuitry, such other circuitry may generate noise in the substrate and/or on the supply lines, which noise may reach the PLL and may disturb its performance, especially its spectral purity. This will lead to unacceptable time jitter in the output signal of the PLL. If the PLL is used in clock signal generation circuitry, excessive quantization noise may be generated in circuits controlled by such clock signals, such as for instance A/D converters.
Therefore, a main object of the present invention is to provide a PLL circuit with improved noise performance.
A well-known technique for making a circuit less sensitive to substrate noise and supply noise is to implement such circuit in a differential architecture. A circuit implemented in differential architecture is not, or only to a little extent, sensitive to common mode signals, while noise on the supply lines and noise in the substrate would couple to the circuit in common mode. Therefore, the effect of such noise in a differential circuit is minimal.
Therefore, a further object of the present invention is to provide a PLL circuit in differential architecture.
An essential component of a PLL is a voltage controlled oscillator (VCO), the output of which is coupled to a phase comparator which compares the output of the VCO with an input signal. A control signal for the VCO is derived from the output signal of the phase comparator. The control input or tuning input of the VCO is, in respect of noise sensitivity, the most important circuit node in a PLL. Typically, the tuning sensitivity of a VCO amounts to several MHz/V. Therefore, even small disturbances that reach the tuning input of the VCO may lead to unacceptably high phase noise side bands (and hence large time jitter).
Therefore, in order to reduce the sensitivity of a PLL with respect to substrate noise and supply noise, especially the VCO tuning part of the PLL circuit should be implemented in a differential architecture.
A block diagram of the general implementation of a PLL, as is commonly known in practice, is schematically depicted in FIG. 1. This PLL circuit 1 comprises a phase comparator 2, a charge pump 3, a VCO 4, and usually a programmable divider 5. The phase comparator 2 has two inputs, one input receiving an input signal SIN, and another input receiving an output signal from the VCO 4 through the programmable divider 5. The phase comparator 2 has two outputs, an UP-output U and a DOWN-output D, coupled to corresponding inputs of the charge pump 3. The charge pump 3 has an output coupled to a tuning input of the VCO 4. Depending on the signal received at said tuning input, the VCO 4 will increase or decrease the frequency of its output signal SOUT.
In the implementation as depicted in the block diagram of FIG. 1, the VCO tuning part of the PLL circuit is implemented in differential architecture, as is commonly known in practice. More particularly, the charge pump 3 has a differential output, and the VCO has a differential tuning input, implicating that the coupling between the charge pump 3 and the VCO comprises two signal lines, as shown specifically. Similarly, the coupling between VCO 4 and programmable divider 5, the output line, the coupling between programmable divider 5 and phase comparator 2, the input line, the coupling between UP-output U of the phase comparator 2 and the corresponding input of the charge pump 3, and the coupling between DOWN-output D of the phase comparator 2 and the corresponding input of the charge pump 3 may all be implemented differentially, in order to provide a fully differential architecture, but this is not shown specifically in FIG. 1.
FIG. 1 also shows two loop filters 71 and 72, connected to the tuning inputs of the VCO, for converting a current output signal of the charge pump 3 into a voltage input signal for the VCO and for increasing stability of the system. Such loop filters are known per se, and will not be discussed further.
If the voltage level at both input terminals of the VCO 4 is changed with the same amount, the output frequency of the VCO 4 will remain constant. Thus, such differential implementation leads to a cleaner VCO output signal as regards common mode substrate noise and supply noise.
However, implementing the VCO tuning part of the PLL circuit in differential architecture will lead to other problems. In comparison with a single-ended implementation of a PLL, where the VCO has only one tuning input coupled to a single-ended charge pump, the VCO now has a differential tuning input receiving two tuning signals, of which the common mode voltage level must be controlled by a common mode feedback circuitry, indicated at 6 in FIG. 1. A basic problem in this respect is the fact that the common mode feedback circuitry 6 constitutes an additional circuitry capable of generating signals on the sensitive tuning inputs of the VCO. Especially, prior art implementations of such common mode feedback circuitry for differential architecture have the important drawback of adding a significant amount of noise to the tuning input of the VCO. This added noise causes unwanted modulation of the VCO and leads to a degradation of the spectral purity. Such noise sources are absent in a single-ended PLL configuration.
Therefore, it is a specific object of the present invention to combine the advantages of having a fully differential implementation of a PLL, having common mode control of the tuning voltage of the VCO, and having a noise level comparable to state of the art single ended PLL implementations.
According to an important aspect of the present invention, the common mode feedback circuitry influences the operation of the charge pump directly. In other words, instead of adding a correction current to the tuning input lines of the VCO, the charge pump generates an amended current.